| Approximate computing: An emerging paradigm for energy-efficient design J Han, M Orshansky 2013 18th IEEE European Test Symposium (ETS), 1-6, 2013 | 1293 | 2013 |
| New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation Y Cao, T Sato, M Orshansky, D Sylvester, C Hu Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE …, 2000 | 724 | 2000 |
| Design for manufacturability and statistical design: a constructive approach M Orshansky, SR Nassif, DS Boning Springer Verlag, 2007 | 306 | 2007 |
| A general probabilistic framework for worst case timing analysis M Orshansky, K Keutzer Proceedings of the 39th annual Design Automation Conference, 556-561, 2002 | 277 | 2002 |
| Bulletproof: A defect-tolerant CMP switch architecture K Constantinides, S Plaza, J Blome, B Zhang, V Bertacco, S Mahlke, ... High-Performance Computer Architecture, 2006. The Twelfth International …, 2006 | 262 | 2006 |
| FASER: Fast analysis of soft error susceptibility for cell-based designs B Zhang, WS Wang, M Orshansky 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-760, 2006 | 236 | 2006 |
| Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits M Orshansky, L Milor, P Chen, K Keutzer, C Hu Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2002 | 215 | 2002 |
| Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization D Nguyen, A Davare, M Orshansky, D Chinnery, B Thompson, K Keutzer Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 213 | 2003 |
| An efficient algorithm for statistical minimization of total power under timing yield constraints M Mani, A Devgan, M Orshansky Proceedings of the 42nd annual Design Automation Conference, 309-314, 2005 | 176 | 2005 |
| Modeling and synthesis of quality-energy optimal approximate adders J Miao, K He, A Gerstlauer, M Orshansky Proceedings of the international conference on computer-aided design, 728-735, 2012 | 169 | 2012 |
| Fast statistical timing analysis handling arbitrary delay correlations M Orshansky, A Bandyopadhyay Proceedings of the 41st annual Design Automation Conference, 337-342, 2004 | 143 | 2004 |
| Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction M Orshansky, L Milor, C Hu Semiconductor Manufacturing, IEEE Transactions on 17 (1), 2-11, 2004 | 140 | 2004 |
| NBTI-aware DVFS: A new approach to saving energy and increasing processor lifetime M Basoglu, M Orshansky, M Erez Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010 | 130 | 2010 |
| Predictive technology model YU Cao, T Sato, D Sylvester, M Orshansky, C Hu Internet: http://ptm. asu. edu, 2002 | 124 | 2002 |
| Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits M Orshansky, L Milor, P Chen, K Keutzer, C Hu Proceedings of the 2000 IEEE/ACM international conference on Computer-aided …, 2000 | 116 | 2000 |
| Analytical modeling of SRAM dynamic stability B Zhang, A Arapostathis, S Nassif, M Orshansky Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 111 | 2006 |
| Approximate logic synthesis under general error magnitude and frequency constraints J Miao, A Gerstlauer, M Orshansky 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 779-786, 2013 | 97 | 2013 |
| Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization M Mani, AK Sing, M Orshansky Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 90 | 2006 |
| A new statistical optimization algorithm for gate sizing M Mani, M Orshansky Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004 …, 2004 | 88 | 2004 |
| Strong subthreshold current array PUF with 265challenge-response pairs resilient to machine learning attacks in 130nm CMOS X Xi, H Zhuang, N Sun, M Orshansky 2017 Symposium on VLSI Circuits, C268-C269, 2017 | 87 | 2017 |
chenming huUniversity of California, BerkeleyVerified email at eecs.berkeley.edu
