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Azadeh Davoodi
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Citado por
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Año
Variability Driven Gate Sizing for Binning Yield Optimization
A Davoodi, A Srivastava
Design Automation Conference, 959-964, 2006
892006
GRIP: Scalable 3D global routing using integer programming
TH Wu, A Davoodi, JT Linderoth
Proceedings of the 46th Annual Design Automation Conference, 320-325, 2009
732009
A hybrid approach for fast and accurate trace signal selection for post-silicon debug
M Li, A Davoodi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
722014
Are proximity attacks a threat to the security of split manufacturing of integrated circuits?
J Magaña, D Shi, J Melchert, A Davoodi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017
592017
A parallel integer programming approach to global routing
TH Wu, A Davoodi, JT Linderoth
Proceedings of the 47th Design Automation Conference, 194-199, 2010
582010
A sensor-assisted self-authentication framework for hardware Trojan detection
M Li, A Davoodi, M Tehranipoor
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
512012
Congestion analysis for global routing via integer programming
H Shojaei, A Davoodi, JT Linderoth
Proceedings of the International Conference on Computer-Aided Design, 256-262, 2011
502011
GRIP: Global routing via integer programming
TH Wu, A Davoodi, JT Linderoth
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2011
502011
A fast and scalable multidimensional multiple-choice knapsack heuristic
H Shojaei, T Basten, M Geilen, A Davoodi
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (4 …, 2013
462013
PaRS: Parallel and near-optimal grid-based cell sizing for library-based design
TH Wu, A Davoodi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
43*2009
A probabilistic approach to buffer insertion
V Khandelwal, A Davoodi, A Nanavati, A Srivastava
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
432003
Representative path selection for post-silicon timing prediction under variability
L Xie, A Davoodi
Proceedings of the 47th Design Automation Conference, 386-391, 2010
422010
FPGA dynamic power minimization through placement and routing constraints
L Wang, M French, A Davoodi, D Agarwal
EURASIP Journal on Embedded Systems 2006, 1-10, 2006
402006
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations
L Xie, A Davoodi, KK Saluja
Proceedings of the 47th Design Automation Conference, 274-279, 2010
38*2010
Trapl: Track planning of local congestion for global routing
D Shi, A Davoodi
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
36*2017
Trace signal selection to enhance timing and logic visibility in post-silicon validation
H Shojaei, A Davoodi
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 168-172, 2010
362010
Bound-based statistically-critical path extraction under process variations
L Xie, A Davoodi
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2011
34*2011
Simultaneous V/sub t/selection and assignment for leakage optimization
V Khandelwal, A Davoodi, A Srivastava
IEEE transactions on very large scale integration (VLSI) systems 13 (6), 762-765, 2005
33*2005
Effective graph theoretic techniques for the generalized low power binding problem
A Davoodi, A Srivastava
Proceedings of the 2003 international symposium on Low power electronics and …, 2003
33*2003
Exploring energy and accuracy tradeoff in structure simplification of trained deep neural networks
B Zhang, A Davoodi, YH Hu
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (4 …, 2018
312018
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Artículos 1–20