| Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators B Reagen, PN Whatmough, R Adolf, S Rama, H Lee, SK Lee, ... International Symposium on Computer Architecture (ISCA), Proceedings of the …, 2016 | 710 | 2016 |
| Federated learning based on dynamic regularization DAE Acar, Y Zhao, RM Navarro, M Mattina, PN Whatmough, V Saligrama arXiv preprint arXiv:2111.04263, 2021 | 474 | 2021 |
| Scale-Sim: Systolic CNN Accelerator Simulator A Samajdar, Y Zhu, PN Whatmough, M Mattina, T Krishna arXiv preprint arXiv:1811.02883, 2018 | 324 | 2018 |
| Ares: A framework for quantifying the resilience of deep neural networks B Reagen, U Gupta, L Pentecost, PN Whatmough, SK Lee, N Mulholland, ... 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018 | 296 | 2018 |
| A 28nm SoC with a 1.2 GHz 568nJ/prediction Sparse Deep-Neural-Network Engine with >0.1 Timing Error Rate Tolerance for IoT Applications PN Whatmough, SK Lee, H Lee, S Rama, D Brooks, GY Wei Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 242-243, 2017 | 195 | 2017 |
| MicroNets: Neural Network Architectures for Deploying tinyML Applications on Commodity Microcontrollers C Banbury, C Zhou, I Fedorov, R Matas, U Thakker, D Gope, ... Proceedings of Machine Learning and Systems 3, 2021 | 190 | 2021 |
| SpArSe: Sparse Architecture Search for CNNs on Resource-Constrained Microcontrollers I Fedorov, RP Adams, M Mattina, P Whatmough Advances in Neural Information Processing Systems (NeurIPS), 4978-4990, 2019 | 150 | 2019 |
| A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim A Samajdar, JM Joseph, Y Zhu, P Whatmough, M Mattina, T Krishna IEEE International Symposium on Performance Analysis of Systems and Software …, 2020 | 117 | 2020 |
| VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter PN Whatmough, MR Perrett, S Isam, I Darwazeh IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) 59 (5 …, 2012 | 109 | 2012 |
| VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter PN Whatmough, MR Perrett, S Isam, I Darwazeh Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, 1688-1691, 2011 | 109 | 2011 |
| Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision Y Zhu, A Samajdar, M Mattina, P Whatmough 45th Annual International Symposium on Computer Architecture (ISCA), 547-560, 2018 | 100 | 2018 |
| DNN ENGINE: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications PN Whatmough, SK Lee, D Brooks, GY Wei IEEE Journal of Solid-State Circuits (JSSC) 53 (9), 2722-2731, 2018 | 96 | 2018 |
| A case for efficient accelerator design space exploration via bayesian optimization B Reagen, JM Hernández-Lobato, R Adolf, M Gelbart, P Whatmough, ... 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 88 | 2017 |
| TinyLSTMs: Efficient neural speech enhancement for hearing aids I Fedorov, M Stamenovic, C Jensen, LC Yang, A Mandell, Y Gan, ... arXiv preprint arXiv:2005.11138, 2020 | 79 | 2020 |
| Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms PN Whatmough, S Das, DM Bull, I Darwazeh IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (6), 989-999, 2013 | 70 | 2013 |
| EdgeBERT: Sentence-level energy optimizations for latency-aware multi-task nlp inference T Tambe, C Hooper, L Pentecost, T Jia, EY Yang, M Donato, V Sanh, ... MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 67 | 2021 |
| FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning PN Whatmough, C Zhou, P Hansen, SK Venkataramanaiah, J Seo, ... The 2nd Conference on Systems and Machine Learning (SysML) 2019, Palo Alto …, 2019 | 63 | 2019 |
| Systolic Tensor Array: An Efficient Structured-Sparse GEMM Accelerator for Mobile CNN Inference ZG Liu, PN Whatmough, M Mattina IEEE Computer Architecture Letters 19 (1), 34-37, 2020 | 57 | 2020 |
| A Low-Power 1GHz Razor FIR Accelerator with Time-Borrow Tracking Pipeline and Approximate Error Correction in 65nm CMOS PN Whatmough, S Das, DM Bull IEEE Journal of Solid-State Circuits (JSSC) 49 (1), 84-94, 2014 | 54 | 2014 |
| A Low-Power 1GHz Razor FIR Accelerator with Time-Borrow Tracking Pipeline and Approximate Error Correction in 65nm CMOS PN Whatmough, S Das, DM Bull International Solid-State Circuits Conference (ISSCC), Digest of Technical …, 2013 | 54 | 2013 |
Matthew MattinaVerified email at alumni.princeton.edu
