Michiko Inoue
Michiko Inoue
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Linear-time snapshot using multi-writer multi-reader registers
M Inoue, T Masuzawa, W Chen, N Tokura
Distributed Algorithms: 8th International Workshop, WDAG'1994 Terschelling …, 1994
A circuit failure prediction mechanism (DART) for high field reliability
Y Sato, S Kajihara, Y Miura, T Yoneda, S Ohtake, M Inoue, H Fujiwara
2009 IEEE 8th International Conference on ASIC, 581-584, 2009
Partial scan approach for secret information protection
M Inoue, T Yoneda, M Hasegawa, H Fujiwara
2009 14th IEEE European Test Symposium, 143-148, 2009
A layout adjustment problem for disjoint rectangles preserving orthogonal order
K Hayashi, M Inoue, T Masuzawa, H Fujiwara
Graph Drawing: 6th International Symposium, GD’98 Montréal, Canada, August …, 1998
Instruction-based self-testing of delay faults in pipelined processors
V Singh, M Inoue, KK Saluja, H Fujiwara
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (11 …, 2006
Classification of Trojan nets based on SCOAP values using supervised learning
CH Kok, CY Ooi, M Moghbel, N Ismail, HS Choo, M Inoue
2019 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2019
DART: Dependable VLSI test architecture and its implementation
Y Sato, S Kajihara, T Yoneda, K Hatayama, M Inoue, Y Miura, S Ohtake, ...
2012 IEEE International Test Conference, 1-10, 2012
Faster-than-at-speed test for increased test quality and in-field reliability
T Yoneda, K Hori, M Inoue, H Fujiwara
2011 IEEE International Test Conference, 1-9, 2011
Instruction-based delay fault self-testing of processor cores
V Singh, M Inoue, KK Saluja, H Fujiwara
17th International Conference on VLSI Design. Proceedings., 933-938, 2004
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation
Y Yamato, T Yoneda, K Hatayama, M Inoue
2012 IEEE International Test Conference, 1-8, 2012
A failure prediction strategy for transistor aging
H Yi, T Yoneda, M Inoue, Y Sato, S Kajihara, H Fujiwara
IEEE transactions on very large scale integration (VLSI) systems 20 (11 …, 2011
Efficient template generation for instruction-based self-test of processor cores
K Kambe, M Inoue, H Fujiwara
13th Asian Test Symposium, 152-157, 2004
Variation-aware hardware Trojan detection through power side-channel
FS Hossain, M Shintani, M Inoue, A Orailoglu
2018 IEEE International Test Conference (ITC), 1-10, 2018
Clustering algorithms in ad hoc networks
H Taniguchi, M Inoue, T Masuzawa, H Fujiwara
IEICE Trans. Inf. & Syst. 84 (2), 127-135, 2001
Net classification based on testability and netlist structural features for hardware Trojan detection
CH Kok, CY Ooi, M Inoue, M Moghbel, SB Dass, HS Choo, N Ismail, ...
2019 IEEE 28th Asian Test Symposium (ATS), 105-1055, 2019
Design for testability of software-based self-test for processors
M Nakazato, S Ohtake, M Inoue, H Fujiwara
2006 15th Asian Test Symposium, 375-380, 2006
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing
T Yoneda, M Inoue, Y Sato, H Fujiwara
2010 28th VLSI Test Symposium (VTS), 188-193, 2010
A snapshot algorithm for distributed mobile systems
Y Sato, M Inoue, T Masuzawa, H Fujiwara
Proceedings of 16th International Conference on Distributed Computing …, 1996
A low power deterministic test using scan chain disable technique
Z You, T Iwagaki, M Inoue, H Fujiwara
IEICE TRANSACTIONS on Information and Systems 89 (6), 1931-1939, 2006
Register-transfer-level features for machine-learning-based hardware trojan detection
HS Choo, CY Ooi, M Inoue, N Ismail, M Moghbel, CH Kok
IEICE Transactions on Fundamentals of Electronics, Communications and …, 2020
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