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Andrew M. Fuller
Andrew M. Fuller
Senior Member of Technical Staff II, Logic Design Engineering, Rambus Inc.
Dirección de correo verificada de afuller.net
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A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS
J Poulton, R Palmer, AM Fuller, T Greer, J Eyles, WJ Dally, M Horowitz
IEEE Journal of Solid-State Circuits 42 (12), 2745-2757, 2007
3212007
Future developments in brain-machine interface research
MA Lebedev, AJ Tate, TL Hanson, Z Li, JE O'Doherty, JA Winans, PJ Ifft, ...
Clinics 66, 25-32, 2011
1572011
A 4.3 GB/s mobile memory interface with power-efficient bandwidth scaling
B Leibowitz, R Palmer, J Poulton, Y Frans, S Li, J Wilson, M Bucher, ...
IEEE Journal of Solid-State Circuits 45 (4), 889-898, 2010
1122010
A 14mW 6.25 Gb/s transceiver in 90nm CMOS for serial chip-to-chip communications
R Palmer, J Poulton, WJ Dally, J Eyles, AM Fuller, T Greer, M Horowitz, ...
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
952007
Edge-based sampler offset correction
AM Fuller, J Poulton, R Inc., V Park, J Joseph
US Patent 8,199,866, 2012
712012
Mesochronous Signaling System with Clock-Stopped Low Power Mode
FA Ware, RE Palmer, JW Poulton, AM Fuller
US Patent 8,918,669, 2014
532014
Subcortical neuronal ensembles: an analysis of motor task association, tremor, oscillations, and synchrony in human patients
TL Hanson, AM Fuller, MA Lebedev, DA Turner, MAL Nicolelis
Journal of Neuroscience 32 (25), 8620-8632, 2012
432012
Latency compensation by horizontal scanline selection for head-mounted displays
J Jerald, A Fuller, A Lastra, M Whitton, L Kohli, F Brooks
Stereoscopic Displays and Virtual Reality Systems XIV 6490, 568-578, 2007
342007
A 4.3 GB/s mobile memory interface with power-efficient bandwidth scaling
R Palmer, J Poulton, B Leibowitz, Y Frans, S Li, A Fuller, J Eyles, J Wilson, ...
2009 Symposium on VLSI Circuits, 136-137, 2009
292009
Mesochronous Signaling System with Core-Clock Synchronization
FA Ware, RE Palmer, JW Poulton, AM Fuller
US Patent 8,918,667, 2014
252014
In-situ delay element calibration
RE Palmer, MD Bucher, AM Fuller
US Patent 9,419,598, 2016
162016
Memory controller with transaction-queue-dependent power modes
FA Ware, RE Palmer, JW Poulton, AM Fuller
US Patent 9,229,523, 2016
152016
Edge-based loss-of-signal detection
AM Fuller, J Poulton, R Inc.
US Patent 8,509,094, 2013
152013
Design considerations for low-power high-performance mobile logic and memory interfaces
R Palmer, J Poulton, A Fuller, J Chen, J Zerbe
2008 IEEE Asian Solid-State Circuits Conference, 205-208, 2008
142008
Memory Controller with Transaction-Queue-Monitoring Power Mode Circuitry
AMF FA Ware, RE Palmer, JW Poulton
US Patent 9,043,633, 2015
11*2015
Signaling interface with phase and framing calibration
FA Ware, RE Palmer, JW Poulton, AM Fuller
US Patent 10,331,193, 2019
102019
Structure and magnetism of Coa (1− x) MnaxGeb epitaxial films
F Tsui, L He, D Lorang, A Fuller, YS Chu, A Tkachuk, S Vogt
Applied surface science 252 (7), 2512-2517, 2006
92006
Low-power clock generation and distribution circuitry
JW Poulton, RE Palmer, AM Fuller, R INC.
US Patent 8,310,294, 2012
62012
Memory IC with data loopback
FA Ware, RE Palmer, JW Poulton, AM Fuller
US Patent 11,556,164, 2023
32023
Clock-forwarding memory controller with mesochronously-clocked signaling interface
FA Ware, RE Palmer, JW Poulton, AM Fuller
US Patent 10,901,485, 2021
12021
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