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Larry Kaplan
Larry Kaplan
Chief Software Architect for HPC
Verified email at hpe.com
Title
Cited by
Cited by
Year
The gemini system interconnect
R Alverson, D Roweth, L Kaplan
High Performance Interconnects (HOTI), 2010 IEEE 18th Annual Symposium on, 83-87, 2010
3502010
Cray XC series network
B Alverson, E Froese, L Kaplan, D Roweth
Cray Inc., White Paper WP-Aries01-1112, 2012
254*2012
Containment domains: A scalable, efficient, and flexible resilience scheme for exascale systems
J Chung, I Lee, M Sullivan, JH Ryoo, DW Kim, DH Yoon, L Kaplan, M Erez
High Performance Computing, Networking, Storage and Analysis (SC), 2012 …, 2012
1322012
Debugging techniques in a multithreaded environment
GA Alverson, BJ Smith, LS Kaplan, ML Niehaus
US Patent 6,480,818, 2002
962002
The robustness of NUMA memory management
RP LaRowe Jr, CS Ellis, LS Kaplan
ACM SIGOPS Operating Systems Review 25 (5), 137-151, 1991
761991
Debugging techniques in a multithreaded environment
GA Alverson, BJ Smith, LS Kaplan, ML Niehaus
US Patent 7,428,727, 2008
632008
Debugging techniques in a multithreaded environment
GA Alverson, BJ Smith, LS Kaplan, ML Niehaus
US Patent 6,848,097, 2005
432005
Event notifications relating to system failures in scalable systems
GA Alverson, RL Alverson, DC Duval, EA Hoffman, LS Kaplan, M Kelly, ...
US Patent 7,984,453, 2011
362011
Cray cnl
L Kaplan
FastOS PI Meeting and Workshop, 2007
322007
Network Performance Counter Monitoring and Analysis on the Cray XC Platform.
JM Brandt, E Froese, AC Gentile, L Kaplan, BA Allan, EJ Walsh
Sandia National Lab.(SNL-CA), Livermore, CA (United States); Sandia National …, 2016
292016
Measuring congestion in high-performance datacenter interconnects
S Jha, A Patke, J Brandt, A Gentile, B Lim, M Showerman, G Bauer, ...
17th {USENIX} Symposium on Networked Systems Design and Implementation …, 2020
262020
Survey of error and fault detection mechanisms
I Lee, M Basoglu, M Sullivan, DH Yoon, L Kaplan, M Erez
University of Texas at Austin, Tech. Rep 11, 12, 2011
262011
Multiprocessor system having processors with different address widths and method for operating the same
M Parker, TJ Johnson, LS Kaplan, SL Scott, R Alverson, S Iterum
US Patent 8,386,750, 2013
23*2013
Resiliency to memory failures in computer systems
LS Kaplan, PP Briggs III, MA Ohlrich, WH Leslie
US Patent 9,535,804, 2017
212017
Techniques for an interrupt free operating system
GA Alverson, IICD Callahan, SL Coatney, LS Kaplan, RD Korry
US Patent 6,314,471, 2001
192001
Techniques for reducing the rate of instruction issuance
GA Alverson, DCII Callahan, SL Coatney, LS Kaplan, RD Korry
US Patent 7,020,767, 2006
162006
Understanding fault scenarios and impacts through fault injection experiments in cielo
V Formicola, S Jha, D Chen, F Deng, A Bonnie, M Mason, J Brandt, ...
arXiv preprint arXiv:1907.01019, 2019
112019
Congestion abatement in a network interconnect
EL Froese, CB Johns, AF Godfrey, LS Kaplan, MP Kelly, BT Shields
US Patent 8,982,688, 2015
112015
CONGESTION ABATEMENT IN A NETWORK INTERCONNECT
EL Froese, CB Johns, AF Godfrey, LS Kaplan, MP Kelly, BT Shields
US Patent 20,120,230,177, 2012
112012
CONGESTION DETECTION IN A NETWORK INTERCONNECT
LS Kaplan, EL Froese, CB Johns, MP Kelly, AF Godfrey, BT Shields
US Patent 20,120,230,212, 2012
112012
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