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Tsutomu Sasao
Tsutomu Sasao
Visiting Professor, Meiji University
Dirección de correo verificada de cs.meiji.ac.jp - Página principal
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Switching theory for logic synthesis
T Sasao
Springer Science & Business Media, 2012
6042012
Logic synthesis and optimization
T Sasao
Kluwer Academic Publishers, 1993
3901993
Representations of discrete functions
T Sasao, M Fujita
Kluwer Academic, 1996
3891996
On the complexity of mod-2l sum PLA's
T Sasao, P Besslich
IEEE Transactions on Computers 39 (2), 262-266, 1990
2791990
Logic synthesis and verification
S Hassoun, T Sasao
Springer Science & Business Media, 2001
2222001
EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions
T Sasao
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993
2151993
Input variable assignment and output phase optimization of PLA's
Sasao
IEEE Transactions on Computers 100 (10), 879-894, 1984
1951984
FPGA design by generalized functional decomposition
T Sasao
Logic synthesis and optimization, 233-258, 1993
1531993
Easily testable realizations for generalized Reed-Muller expressions
T Sasao
IEEE transactions on computers 46 (6), 709-716, 1997
1241997
Memory-based logic synthesis
T Sasao
Springer Science & Business Media, 2011
1232011
Multiple-valued decomposition of generalized Boolean functions and the complexity of programmable logic arrays
Sasao
IEEE Transactions on computers 100 (9), 635-643, 1981
1201981
AND-EXOR expressions and their optimization
T Sasao
Logic synthesis and optimization, 287-312, 1993
1181993
Representations of logic functions using EXOR operators
T Sasao
Representations of discrete functions, 29-54, 1996
1041996
On the optimal design of multiple-valued PLAs
T Sasao
IEEE Transactions on Computers 38 (4), 582-592, 1989
1001989
A method to represent multiple-output switching functions by using multi-valued decision diagrams
T Sasao, JT Butler
Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic …, 1996
971996
Numerical function generators using LUT cascades
T Sasao, S Nagayama, JT Butler
IEEE Transactions on Computers 56 (6), 826-838, 2007
922007
A cascade realization of multiple-output function for reconfigurable hardware
T Sasao, M Matsuura, Y Iguchi
International Workshop on Logic and Synthesis (IWLS01), 12-15, 2001
922001
Selection of potentially testable path delay faults for test generation
A Murakami, S Kajihara, T Sasao, I Pomeranz, SM Reddy
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000
902000
Ternary decision diagrams. Survey
T Sasao
Proceedings 1997 27th International Symposium on Multiple-Valued Logic, 241-250, 1997
841997
A deep convolutional neural network based on nested residue number system
H Nakahara, T Sasao
2015 25th International Conference on Field Programmable Logic and …, 2015
772015
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Artículos 1–20