| Pond: Cxl-based memory pooling systems for cloud platforms H Li, DS Berger, L Hsu, D Ernst, P Zardoshti, S Novakovic, M Shah, ... Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 123 | 2023 |
| First-generation memory disaggregation for cloud platforms H Li, DS Berger, S Novakovic, L Hsu, D Ernst, P Zardoshti, M Shah, ... arXiv preprint arXiv:2203.00241, 2022 | 39 | 2022 |
| Optimizing persistent memory transactions P Zardoshti, T Zhou, Y Liu, M Spear 2019 28th International Conference on Parallel Architectures and Compilation …, 2019 | 20 | 2019 |
| Adaptive sparse matrix representation for efficient matrix–vector multiplication P Zardoshti, F Khunjush, H Sarbazi-Azad The Journal of Supercomputing 72 (9), 3366-3386, 2016 | 20 | 2016 |
| Simplifying transactional memory support in c++ P Zardoshti, T Zhou, P Balaji, ML Scott, M Spear ACM Transactions on Architecture and Code Optimization (TACO) 16 (3), 1-24, 2019 | 15 | 2019 |
| Design tradeoffs in cxl-based memory pools for public cloud platforms DS Berger, D Ernst, H Li, P Zardoshti, M Shah, S Rajadnya, S Lee, L Hsu, ... IEEE Micro 43 (2), 30-38, 2023 | 14 | 2023 |
| Practical experience with transactional lock elision T Zhou, PA Zardoshti, M Spear 2017 46th International Conference on Parallel Processing (ICPP), 81-90, 2017 | 14 | 2017 |
| Understanding and improving persistent transactions on optane™ DC memory P Zardoshti, M Spear, A Vosoughi, G Swart 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2020 | 13 | 2020 |
| SPX64: A scratchpad memory for general-purpose microprocessors A Singh, S Dave, P Zardoshti, R Brotzman, C Zhang, X Guo, ... ACM Transactions on Architecture and Code Optimization (TACO) 18 (1), 1-26, 2020 | 8 | 2020 |
| Brief announcement: Optimizing persistent transactions T Zhou, P Zardoshti, M Spear ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), 169-170, 2019 | 3 | 2019 |
| Critical Section Speedup Using Help-Enabled Locks Y Lev, VM Luchangco, D Dice, A Kogan, TL Harris, P Zardoshti US Patent App. 18/515,027, 2024 | | 2024 |
| Critical section speedup using help-enabled locks Y Lev, VM Luchangco, D Dice, A Kogan, TL Harris, P Zardoshti US Patent 11,861,416, 2024 | | 2024 |
| Critical section speedup using help-enabled locks Y Lev, VM Luchangco, D Dice, A Kogan, TL Harris, P Zardoshti US Patent 11,068,319, 2021 | | 2021 |
| Language Level Support for Persistent Memory P Zardoshti Lehigh University, 2021 | | 2021 |
| Optimizing Persistent Transactions (Brief Announcement) T Zhou, P Zardoshti, M Spear The 31st ACM Symposium on Parallelism in Algorithms and Architectures, 169-170, 2019 | | 2019 |
| Lightweight Language-Level Support for Transactional Memory P Zardoshti, M Spear Programming Language Design and Implementation (PLDI), 2018 | | 2018 |
| Universal Support for Scoped Memory Access Instrumentation P Zardoshti, M Spear | | |
Michael SpearLehigh UniversityVerified email at cse.lehigh.edu
