| Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes MT Moreira, RA Guazzelli, NLV Calazans 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2012 | 52 | 2012 |
| ASCEnD-FreePDK45: An open source standard cell library for asynchronous design CHM Oliveira, MT Moreira, RA Guazzelli, NLV Calazans 2016 IEEE International Conference on Electronics, Circuits and Systems …, 2016 | 16 | 2016 |
| HardNoC: A platform to validate networks on chip through FPGA prototyping G Heck, R Guazzelli, F Moraes, N Calazans, R Soares 2012 VIII southern conference on programmable logic, 1-6, 2012 | 16 | 2012 |
| Return-to-One DIMS Logic on 4-phase m-of-n Asynchronous Circuits MT Moreira, RA Guazzelli, NLV Calazans 2012 19th IEEE International Conference on Electronics, Circuits, and …, 2012 | 15 | 2012 |
| Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis MT Moreira, RA Guazzelli, G Heck, NLV Calazans Proceedings of the 24th edition of the great lakes symposium on VLSI, 3-8, 2014 | 11 | 2014 |
| A new CMOS topology for low-voltage null convention logic gates design MT Moreira, ME Arendt, RA Guazzelli, NLV Calazans 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems …, 2014 | 9 | 2014 |
| A comparison of asynchronous QDI templates using static logic RA Guazzelli, MT Moreira, NLV Calazans 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2017 | 6 | 2017 |
| Trojan detection test for clockless circuits RA Guazzelli, MG Trindade, LA Guimaraes, TF de Paiva Leite, L Fesquet, ... Journal of Electronic Testing 36, 23-31, 2020 | 5 | 2020 |
| Sleep convention logic isochronic fork: An analysis RA Guazzelli, MT Moreira, WL Neto, NLV Calazans Proceedings of the 30th Symposium on Integrated Circuits and Systems Design …, 2017 | 3 | 2017 |
| Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough? R Guazzelli, G Heck, M Moreira, N Calazans 2014 15th Latin American Test Workshop-LATW, 1-5, 2014 | 3 | 2014 |
| At-speed DfT Architecture for Bundled-data Design RA Guazzelli, L Fesquet 2020 IEEE International Test Conference (ITC), 1-9, 2020 | 2 | 2020 |
| SDDS-NCL design: Analysis of supply voltage scaling RA Guazzelli, FG Moraes, NLV Calazans, MT Moreira Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 1-7, 2015 | 2 | 2015 |
| Learning-based reliability assessment method for detection of permanent faults in clockless circuits RA Guazzelli, MG Trindade, L Fesquet, RP Bastos Microelectronics Reliability 100, 113365, 2019 | 1 | 2019 |
| test and side-channel analysis of asynchronous circuits RA Guazzelli Université Grenoble Alpes [2020-....], 2020 | | 2020 |
| Exploring a Non-conventional Testing Technique for Asynchronous Circuits RA Guazzelli, MG Trindade, L Fesquet, RP Bastos 21èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM 2019), 2019 | | 2019 |
| SDDS-NCL Design RA Guazzelli, FG Moraes, NLV Calazans, MT Moreira Proceedings of the 28th Symposium on Integrated Circuits and Systems Design …, 2015 | | 2015 |
| VOLTAGE SCALING EFFECTS ON NCL CELLS: Analysis and Characterization RA GUAZZELLI | | 2015 |
| Analysis of Supply Voltage Scaling on SDDS-NCL Design NLV Calazans, MT Moreira, FG Moraes, R Guazzelli SBCCI, 2015, Brasil., 2015 | | 2015 |
Ney Laert Vilar CalazansInvited Researcher at the Graduate Program on Microelectronics (PGMICRO), UFRGSVerified email at inf.ufrgs.br
