| Spiker: an fpga-optimized hardware accelerator for spiking neural networks A Carpegna, A Savino, S Di Carlo 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 14-19, 2022 | 21 | 2022 |
| Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study D Kasap, A Carpegna, A Savino, S Di Carlo 2023 IEEE European Test Symposium (ETS), 1-5, 2023 | 5 | 2023 |
| Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge A Carpegna, A Savino, S Di Carlo arXiv preprint arXiv:2401.01141, 2024 | 3 | 2024 |
| EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS F Pavanello, C Marchand, I O’Connor, R Orobtchouk, F Mandorlo, ... 2023 IEEE European Test Symposium (ETS), 1-6, 2023 | 2 | 2023 |
| Artificial resilience in neuromorphic systems A Carpegna, S Di Carlo, A Savino Proceedings of the 12th International Symposium on Highly-Efficient …, 2022 | 2 | 2022 |
| Fpga-optimized hardware acceleration for spiking neural networks A Carpegna, A Savino, S Di Carlo arXiv preprint arXiv:2201.06993, 2022 | 2 | 2022 |
| Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies F Pavanello, EI Vatajelu, A Bosio, T Van Vaerenbergh, P Bienstman, ... 2023 IEEE 41st VLSI Test Symposium (VTS), 1-10, 2023 | 1 | 2023 |
| Design of an hardware accelerator for a Spiking Neural Network. A Carpegna Politecnico di Torino, 2021 | 1 | 2021 |
| SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA D Padovano, A Carpegna, A Savino, S Di Carlo arXiv preprint arXiv:2404.03714, 2024 | | 2024 |
| SpikingJET: Enhancing Fault Injection for Fully and Convolutional Spiking Neural Networks AB Gogebakan, E Magliano, A Carpegna, A Ruospo, A Savino, S Di Carlo arXiv preprint arXiv:2404.00383, 2024 | | 2024 |
| SpikingJET: Enhancing Fault Injection for Fully and Convolutional Spiking Neural Networks A Bayram Gogebakan, E Magliano, A Carpegna, A Ruospo, A Savino, ... arXiv e-prints, arXiv: 2404.00383, 2024 | | 2024 |
| A Micro Architectural Events Aware Real-Time Embedded System Fault Injector E Magliano, A Carpegna, A Savino, S Di Carlo arXiv preprint arXiv:2401.08397, 2024 | | 2024 |
| Fast Exploration of the Impact of Precision Reduction on Spiking Neural Networks S Saeedi, A Carpegna, A Savino, S Di Carlo arXiv preprint arXiv:2212.11782, 2022 | | 2022 |
| Prediction of the Impact of Approximate Computing on Spiking Neural Networks via Interval Arithmetic S Saeedi, A Carpegna, A Savino, S Di Carlo 2022 IEEE 23rd Latin American Test Symposium (LATS), 1-6, 2022 | | 2022 |
| Spiking Neural Network Data Reduction via Interval Arithmetic S Saeedi, A Carpegna, A Savino, S Di Carlo Proceedings of the 18th IEEE Workshop on Silicon Errors in Logic–System …, 2022 | | 2022 |
| Are micro-architectural features able to explain faulty executions in the presence of soft errors? A preliminary study. D Kasap, A Carpegna, A Savino, S Di Carlo CoRR, 2022 | | 2022 |
| 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)| 978-1-6654-6605-9/22/$31.00© 2022 IEEE| DOI: 10.1109/ISVLSI54635. 2022.00103 H Abunahla, T Adegbija, F Afghah, S Agarwal, S Ahlawat, QA Ahmed, ... | | |
| ISVLSI 2022 A Carpegna, A Savino | | |
Stefano Di CarloFull Professor, Politecnico di TorinoDirección de correo verificada de polito.it
