Eugenio Culurciello
Cited by
Cited by
Enet: A deep neural network architecture for real-time semantic segmentation
A Paszke, A Chaurasia, S Kim, E Culurciello
arXiv preprint arXiv:1606.02147, 2016
Linknet: Exploiting encoder representations for efficient semantic segmentation
A Chaurasia, E Culurciello
2017 IEEE visual communications and image processing (VCIP), 1-4, 2017
An analysis of deep neural network models for practical applications
A Canziani, A Paszke, E Culurciello
arXiv preprint arXiv:1605.07678, 2016
Neuflow: A runtime reconfigurable dataflow processor for vision
C Farabet, B Martini, B Corda, P Akselrod, E Culurciello, Y LeCun
CVPR 2011 workshops, 109-116, 2011
A biomorphic digital image sensor
E Culurciello, R Etienne-Cummings, KA Boahen
IEEE journal of solid-state circuits 38 (2), 281-294, 2003
A 240 g-ops/s mobile coprocessor for deep neural networks
V Gokhale, J Jin, A Dundar, B Martini, E Culurciello
Proceedings of the IEEE conference on computer vision and pattern …, 2014
Hardware accelerated convolutional neural networks for synthetic vision systems
C Farabet, B Martini, P Akselrod, S Talay, Y LeCun, E Culurciello
Proceedings of 2010 IEEE international symposium on circuits and systems …, 2010
Flattened convolutional neural networks for feedforward acceleration
J Jin, A Dundar, E Culurciello
arXiv preprint arXiv:1412.5474, 2014
Spatially compact neural clusters in the dorsal striatum encode locomotion relevant information
G Barbera, B Liang, L Zhang, CR Gerfen, E Culurciello, R Chen, Y Li, ...
Neuron 92 (1), 202-213, 2016
Activity-driven, event-based vision sensors
T Delbrück, B Linares-Barranco, E Culurciello, C Posch
Proceedings of 2010 IEEE international symposium on circuits and systems …, 2010
Recurrent neural networks hardware implementation on FPGA
AXM Chang, B Martini, E Culurciello
arXiv preprint arXiv:1511.05552, 2015
Capacitive inter-chip data and power transfer for 3-D VLSI
E Culurciello, AG Andreou
IEEE Transactions on Circuits and Systems II: Express Briefs 53 (12), 1348-1352, 2006
Large-scale FPGA-based convolutional networks
C Farabet, Y LeCun, K Kavukcuoglu, E Culurciello, B Martini, P Akselrod, ...
Scaling up machine learning: parallel and distributed approaches 13 (3), 399-419, 2011
Hardware accelerators for recurrent neural networks on FPGA
AXM Chang, E Culurciello
2017 IEEE International symposium on circuits and systems (ISCAS), 1-4, 2017
Embedded streaming deep neural networks accelerator with applications
A Dundar, J Jin, B Martini, E Culurciello
IEEE transactions on neural networks and learning systems 28 (7), 1572-1583, 2016
NeuFlow: Dataflow vision processing system-on-a-chip
PH Pham, D Jelaca, C Farabet, B Martini, Y LeCun, E Culurciello
2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012
Snowflake: An efficient hardware accelerator for convolutional neural networks
V Gokhale, A Zaidy, AXM Chang, E Culurciello
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
An address-event fall detector for assisted living applications
Z Fu, T Delbruck, P Lichtsteiner, E Culurciello
IEEE transactions on biomedical circuits and systems 2 (2), 88-96, 2008
A multichip neuromorphic system for spike-based visual information processing
RJ Vogelstein, U Mallik, E Culurciello, G Cauwenberghs, ...
Neural computation 19 (9), 2281-2300, 2007
Noise analysis and performance comparison of low current measurement systems for biomedical applications
D Kim, B Goldstein, W Tang, FJ Sigworth, E Culurciello
IEEE transactions on biomedical circuits and systems 7 (1), 52-62, 2012
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