| Developing synthesis flows without human knowledge C Yu, H Xiao, G De Micheli Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 91 | 2018 |
| Verification of gate-level arithmetic circuits by function extraction M Ciesielski, C Yu, W Brown, D Liu, A Rossi Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 84 | 2015 |
| Painting on placement: Forecasting routing congestion using conditional generative adversarial nets C Yu, Z Zhang Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 81 | 2019 |
| Incremental SAT-based reverse engineering of camouflaged logic circuits C Yu, X Zhang, D Liu, M Ciesielski, D Holcomb IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 81 | 2017 |
| Formal verification of arithmetic circuits by function extraction C Yu, W Brown, D Liu, A Rossi, M Ciesielski IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 63 | 2016 |
| Fast algebraic rewriting based on and-inverter graphs C Yu, M Ciesielski, A Mishchenko IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 60 | 2017 |
| Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits D Liu, C Yu, X Zhang, D Holcomb 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 433-438, 2016 | 57 | 2016 |
| Understanding algebraic rewriting for arithmetic circuit verification: a bit-flow model M Ciesielski, T Su, A Yasin, C Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 46 | 2019 |
| Real-time multi-task diffractive deep neural networks via hardware-software co-design Y Li, R Chen, B Sensale-Rodriguez, W Gao, C Yu Scientific reports 11 (1), 11013, 2021 | 39 | 2021 |
| LAMDA: Learning-assisted multi-stage autotuning for FPGA design closure E Ustun, S Xiang, J Gui, C Yu, Z Zhang 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019 | 38 | 2019 |
| Logic synthesis meets machine learning: Trading exactness for generalization S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 29 | 2021 |
| Flowtune: Practical multi-armed bandits in boolean optimization C Yu Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 29 | 2020 |
| Decision making in synthesis cross technologies using LSTMs and transfer learning C Yu, W Zhou Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD, 55-60, 2020 | 27 | 2020 |
| Logic debugging of arithmetic circuits S Ghandali, C Yu, D Liu, W Brown, M Ciesielski 2015 IEEE Computer Society Annual Symposium on VLSI, 113-118, 2015 | 27 | 2015 |
| Efficient parallel verification of galois field multipliers C Yu, M Ciesielski 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 238-243, 2017 | 22 | 2017 |
| Automatic word-level abstraction of datapath C Yu, M Ciesielski 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1718-1721, 2016 | 21 | 2016 |
| Read your circuit: Leveraging word embedding to guide logic optimization WL Neto, MT Moreira, L Amaru, C Yu, PE Gaillardon Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 18 | 2021 |
| SLAP: A supervised learning approach for priority cuts technology mapping WL Neto, MT Moreira, Y Li, L Amarù, C Yu, PE Gaillardon 2021 58th ACM/IEEE Design Automation Conference (DAC), 859-864, 2021 | 16 | 2021 |
| Formal analysis of Galois field arithmetic circuits-parallel verification and reverse engineering C Yu, M Ciesielski IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 16* | 2018 |
| Analyzing Imprecise Adders Using BDDs--A Case Study C Yu, M Ciesielski 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 152-157, 2016 | 16 | 2016 |
