Julian Pontes
Julian Pontes
Verified email at
Cited by
Cited by
IntAct: A 96-core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management
P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, C Fuguet, I Miro-Panades, ...
IEEE Journal of Solid-State Circuits 56 (1), 79-97, 2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm …
P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, G Moritz, I Miro-Panadès, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 46-48, 2020
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
J Pontes, R Soares, E Carvalho, F Moraes, N Calazans
2007 25th International Conference on Computer Design, 541-546, 2007
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design
M Moreira, B Oliveira, J Pontes, N Calazans
2011 IEEE International SOC Conference, 99-104, 2011
Hermes-glp: A gals network on chip router with power control techniques
J Pontes, M Moreira, R Soares, N Calazans
2008 IEEE Computer Society Annual Symposium on VLSI, 347-352, 2008
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing
JJH Pontes, MT Moreira, FG Moraes, NLV Calazans
23rd IEEE International SOC Conference, 493-498, 2010
Hermes-A–an asynchronous NoC router with distributed routing
J Pontes, M Moreira, F Moraes, N Calazans
Integrated Circuit and System Design. Power and Timing Modeling …, 2011
Adapting a C-element design flow for low power
M Moreira, B Oliveira, J Pontes, F Moraes, N Calazans
2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011
An accurate single event effect digital design flow for reliable system level design
J Pontes, N Calazans, P Vivet
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 224-229, 2012
Adding temporal redundancy to delay insensitive codes to mitigate single event effects
J Pontes, N Calazans, P Vivet
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems …, 2012
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design
MT Moreira, JJH Pontes, NLV Calazans
Fifteenth International Symposium on Quality Electronic Design, 692-699, 2014
Two-phase protocol converters for 3D asynchronous 1-of-n data links
J Pontes, P Vivet, Y Thonnart
The 20th Asia and South Pacific Design Automation Conference, 154-159, 2015
Soft error mitigation in asynchronous networks on chip
JJH Pontes
Pontifícia Universidade Católica do Rio Grande do Sul, 2012
Projeto e prototipação de interfaces e redes intrachip não-síncronas em FGPAs
JJH Pontes
Pontifícia Universidade Católica do Rio Grande do Sul, 2008
Parity check for m-of-n delay insensitive codes
J Pontes, N Calazans, P Vivet
2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 157-162, 2013
H2A: A hardened asynchronous network on chip
J Pontes, N Calazans, P Vivet
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
Automated versus Manual Design of Asynchronous Circuits in DSM Technologies
M Moreira, B Oliveira, J Pontes, N Calazans
Multiprocessor System on a Chip
S Johann Filho, J Pontes, V Leithardt
Projeto de Sistemas Digitais utilizando a Metodologia GALS
MT Moreira, J Pontes, N Calazans
ISVLSI 2012 Additional Reviewers
A Amory, A Reis, A Gupta, A Papanikolaou, B Allard, C Weis, ...
The system can't perform the operation now. Try again later.
Articles 1–20