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Sina Tolouei
Sina Tolouei
Carleton University
Verified email at sce.carleton.ca
Title
Cited by
Cited by
Year
Lowering the error floor of LDPC codes using multi-step quantization
S Tolouei, AH Banihashemi
IEEE communications letters 18 (1), 86-89, 2013
162013
Fast and accurate error floor estimation of quantized iterative decoders for variable-regular LDPC codes
S Tolouei, AH Banihashemi
IEEE communications letters 18 (8), 1283-1286, 2014
152014
Successive relaxation for decoding of LDPC codes
H Xiao, S Tolouei, AH Banihashemi
2008 24th Biennial Symposium on Communications, 107-110, 2008
102008
FPGA implementation of variants of min-sum algorithm
S Tolouei, AH Banihashemi
2008 24th Biennial Symposium on Communications, 80-83, 2008
52008
High Speed Low Error Floor Hardware Implementation and Fast and Accurate Error Floor Estimation of LDPC Decoders
S Tolouei
Carleton University, 2014
22014
Design and FPGA implementation of Min-Sum algorithm and its variants
S Tolouei
Carleton University, 2008
12008
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Articles 1–6