| Hierarchical verification for equivalence checking of designs L McIlwain, D Anastasakis, S Pilarski US Patent 6,668,362, 2003 | 23 | 2003 |
| Reducing x-pessimism in gate-level simulation and verification A Salz, GR Maturana, IH Moon, LR McIlwain US Patent 8,650,513, 2014 | 14 | 2014 |
| Efficient equivalence checking with partitions and hierarchical cut-points D Anastasakis, L McIlwain, S Pilarski Proceedings of the 41st annual Design Automation Conference, 539-542, 2004 | 8 | 2004 |
| Concurrent formal verification of logic synthesis LR McIlwain, MS Quayle, E Odiz, P Groeneveld, JW Hagerman, ... US Patent 10,643,012, 2020 | 1 | 2020 |
| Formal gated clock conversion for field programmable gate array (FPGA) synthesis L McIlwain, F Rahim, G Plassan, DR Senapati US Patent 11,526,641, 2022 | | 2022 |
