| In-datacenter performance analysis of a tensor processing unit NP Jouppi, C Young, N Patil, D Patterson, G Agrawal, R Bajwa, S Bates, ... Proceedings of the 44th annual international symposium on computer …, 2017 | 4825 | 2017 |
| McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures S Li, JH Ahn, RD Strong, JB Brockman, DM Tullsen, NP Jouppi Proceedings of the 42nd annual ieee/acm international symposium on …, 2009 | 3159 | 2009 |
| Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers NP Jouppi ACM SIGARCH Computer Architecture News 18 (2SI), 364-373, 1990 | 2279 | 1990 |
| Complexity-effective superscalar processors S Palacharla, NP Jouppi, JE Smith Proceedings of the 24th annual international symposium on Computer …, 1997 | 1300 | 1997 |
| Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory X Dong, C Xu, Y Xie, NP Jouppi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 1281 | 2012 |
| CACTI 6.0: A tool to model large caches N Muralimanohar, R Balasubramonian, NP Jouppi HP laboratories 27, 28, 2009 | 1163 | 2009 |
| Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction R Kumar, KI Farkas, NP Jouppi, P Ranganathan, DM Tullsen Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003 | 1097 | 2003 |
| Cacti 3.0: An integrated cache timing, power, and area model P Shivakumar, NP Jouppi Technical Report 2001/2, Compaq Computer Corporation, 2001 | 1068 | 2001 |
| CACTI: An enhanced cache access and cycle time model SJE Wilton, NP Jouppi IEEE Journal of solid-state circuits 31 (5), 677-688, 1996 | 1062 | 1996 |
| Corona: System implications of emerging nanophotonic technology D Vantrease, R Schreiber, M Monchiero, M McLaren, NP Jouppi, ... ACM SIGARCH Computer Architecture News 36 (3), 153-164, 2008 | 879 | 2008 |
| Single-ISA heterogeneous multi-core architectures for multithreaded workload performance R Kumar, DM Tullsen, P Ranganathan, NP Jouppi, KI Farkas ACM SIGARCH Computer Architecture News 32 (2), 64, 2004 | 871 | 2004 |
| CACTI 5.1 S Thoziyoor, N Muralimanohar, JH Ahn, NP Jouppi Technical Report HPL-2008-20, HP Labs, 2008 | 818 | 2008 |
| Available instruction-level parallelism for superscalar and superpipelined machines NP Jouppi, DW Wall ACM SIGARCH Computer Architecture News 17 (2), 272-282, 1989 | 566 | 1989 |
| Heterogeneous chip multiprocessors R Kumar, DM Tullsen, NP Jouppi, P Ranganathan Computer 38 (11), 32-38, 2005 | 502 | 2005 |
| An enhanced access and cycle time model for on-chip caches SJE Wilton WRL Research Report, 1994 | 499 | 1994 |
| Dynamically selecting processor cores for overall power efficiency K Farkas, NP Jouppi, RN Mayo, P Ranganathan US Patent 7,093,147, 2006 | 456 | 2006 |
| Reconfigurable caches and their application to media processing P Ranganathan, S Adve, NP Jouppi ACM SIGARCH Computer Architecture News 28 (2), 214-224, 2000 | 397 | 2000 |
| CACTI 4.0 D Tarjan, S Thoziyoor, NP Jouppi Technical Report HPL-2006-86, HP Laboratories Palo Alto, 2006 | 394 | 2006 |
| System and method for displaying images using anamorphic video NP Jouppi US Patent 6,549,215, 2003 | 383 | 2003 |
| The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays MS Hrishikesh, D Burger, NP Jouppi, SW Keckler, KI Farkas, ... ACM SIGARCH Computer Architecture News 30 (2), 14-24, 2002 | 366 | 2002 |
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