Follow
Ananda Samajdar
Ananda Samajdar
Staff Research Scientist, IBM Research
Verified email at ibm.com - Homepage
Title
Cited by
Cited by
Year
MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Programmable Interconnects
H Kwon, A Samajdar, T Krishna
Sysml, 2018
530*2018
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training
E Qin, A Samajdar, H Kwon, V Nadella, S Srinivasan, D Das, B Kaul, ...
International Symposium on High Performance Computer Architecture, 2020
4512020
SCALE-Sim: Systolic CNN Accelerator Simulator
A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna
arXiv preprint arXiv:1811.02883, 2018
3112018
A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim
A Samajdar, JM Joseph, Y Zhu, P Whatmough, M Mattina, T Krishna
2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020
1892020
Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision
Y Zhu, A Samajdar, M Mattina, P Whatmough
International Symposium on Computer Architecture, 2018
1102018
Scale-sim: Systolic CNN accelerator
A Samajdar, Y Zhu, PN Whatmough, M Mattina, T Krishna
arXiv preprint arXiv:1811.02883 57, 2018
882018
Rethinking NoCs for spatial neural network accelerators
H Kwon, A Samajdar, T Krishna
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on …, 2017
862017
Scaling the Cascades: Interconnect-aware FPGA implementation of Machine Learning problems
A Samajdar, T Garg, T Krishna, N Kapre
29th International Conference on Field Programmable Logic and Applications (FPL), 2019
262019
GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware
A Samajdar, P Mannan, K Garg, T Krishna
The 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018
242018
Data orchestration in deep learning accelerators
T Krishna, H Kwon, A Parashar, M Pellauer, A Samajdar
Morgan & Claypool Publishers 15, 1-164, 2020
202020
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU
TK Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes ...
58th Annual Design Automation Conference (DAC), 2021
18*2021
A communication-centric approach for designing flexible DNN accelerators
H Kwon, A Samajdar, T Krishna
IEEE Micro 38 (6), 25-35, 2018
142018
Self adaptive reconfigurable arrays (SARA) learning flexible GEMM accelerator configuration and mapping-space using ML
A Samajdar, E Qin, M Pellauer, T Krishna
Proceedings of the 59th ACM/IEEE Design Automation Conference, 583-588, 2022
122022
Architecture, dataflow and physical design implications of 3D-ICs for DNN-accelerators
JM Joseph, A Samajdar, L Zhu, R Leupers, SK Lim, T Pionteck, T Krishna
2021 22nd International Symposium on Quality Electronic Design (ISQED), 60-66, 2021
112021
Scale-sim: Systolic cnn accelerator simulator. arXiv 2018
A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna
arXiv preprint arXiv:1811.02883, 0
10
AIRCHITECT: Learning custom architecture design and mapping space
A Samajdar, JM Joseph, M Denton, T Krishna
arXiv preprint arXiv:2108.08295, 2021
62021
Self-adaptive reconfigurable arrays (sara): Using ml to assist scaling gemm acceleration
A Samajdar, M Pellauer, T Krishna
arXiv preprint arXiv:2101.04799, 2021
42021
Towards cognitive ai systems: Workload and characterization of neuro-symbolic ai
Z Wan, CK Liu, H Yang, R Raj, C Li, H You, Y Fu, C Wan, A Samajdar, ...
2024 IEEE International Symposium on Performance Analysis of Systems and …, 2024
22024
AIrchitect: Automating Hardware Architecture and Mapping Optimization
A Samajdar, JM Joseph, T Krishna
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023
22023
Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture
Z Wan, CK Liu, H Yang, R Raj, C Li, H You, Y Fu, C Wan, S Li, Y Kim, ...
IEEE Transactions on Circuits and Systems for Artificial Intelligence, 2024
12024
The system can't perform the operation now. Try again later.
Articles 1–20