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Ricardo Martins
Ricardo Martins
Instituto de Telecomunicações, Instituto Superior Técnico - Universidade de Lisboa
Verified email at lx.it.pt - Homepage
Title
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Cited by
Year
LAYGEN II—automatic layout generation of analog integrated circuits
R Martins, N Lourenco, N Horta
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2013
1072013
Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
E Afacan, N Lourenço, R Martins, G Dündar
Integration 77, 113-130, 2021
742021
Using artificial neural networks for analog integrated circuit design automation
JPS Rosa, DJD Guerra, NCG Horta, FM Martins, NCC Lourenço
Springer, 2020
52*2020
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation
N Lourenço, R Martins, A Canelas, R Povoa, N Horta
Integration 55, 316-329, 2016
522016
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction
N Lourenço, R Martins, N Horta
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
492015
AIDA: Automated analog IC design flow from circuit level to layout
R Martins, N Lourenço, S Rodrigues, J Guilherme, N Horta
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
482012
Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
N Lourenço, R Martins, N Horta
Springer International Publishing, 2017
452017
Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates
R Martins, N Lourenço, N Horta
Expert Systems with Applications 42 (23), 9137-9151, 2015
402015
AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation
R Martins, N Lourenço, A Canelas, R Póvoa, N Horta
2015 International Conference on Synthesis, Modeling, Analysis and …, 2015
392015
Many-objective sizing optimization of a class-C/D VCO for ultralow-power IoT and ultralow-phase-noise cellular applications
R Martins, N Lourenco, N Horta, J Yin, PI Mak, RP Martins
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 69-82, 2018
382018
Floorplan-aware analog IC sizing and optimization based on topological constraints
N Lourenço, A Canelas, R Póvoa, R Martins, N Horta
Integration 48, 183-197, 2015
382015
Two-step RF IC block synthesis with preoptimized inductors and full layout generation in-the-loop
R Martins, N Lourenço, F Passos, R Póvoa, A Canelas, E Roca, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
372018
Using polynomial regression and artificial neural networks for reusable analog IC sizing
N Lourenço, E Afacan, R Martins, F Passos, A Canelas, R Póvoa, N Horta, ...
2019 16th International Conference on Synthesis, Modeling, Analysis and …, 2019
312019
On the exploration of promising analog ic designs via artificial neural networks
N Lourenço, J Rosa, R Martins, H Aidos, A Canelas, R Póvoa, N Horta
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
302018
Electronic design automation of analog ICs combining gradient models with multi-objective evolutionary algorithms
FAE Rocha, RMF Martins, NCC Lourenço, NCG Horta
Springer Science & Business Media, 2013
29*2013
Electromigration-aware analog Router with multilayer multiport terminal structures
R Martins, N Lourenco, A Canelas, N Horta
Integration 47 (4), 532-547, 2014
282014
Design of a 4.2-to-5.1 GHz ultralow-power complementary class-B/C hybrid-mode VCO in 65-nm CMOS fully supported by EDA tools
R Martins, N Lourenço, N Horta, S Zhong, J Yin, PI Mak, RP Martins
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3965-3977, 2020
272020
FUZYE: A Fuzzy -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms
A Canelas, R Póvoa, R Martins, N Lourenço, J Guilherme, JP Carvalho, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
272018
Analog Integrated Circuit Design Automation
R Martins, N Lourenço, N Horta
Cham, Switzerland: Springer, 2017
272017
Single-stage amplifier biased by voltage combiners with gain and energy-efficiency enhancement
R Povoa, N Lourenco, R Martins, A Canelas, NCG Horta, J Goes
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (3), 266-270, 2017
262017
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