Somayeh Timarchi

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Omid KaveheiThe University of SydneyDirección de correo verificada de sydney.edu.au
Mahmood FazlaliLecturer, University of hertfordshire, Shahid Beheshti University, TUDelftDirección de correo verificada de herts.ac.uk
Vahid ForoutanPhD - University of Illinois ChicagoDirección de correo verificada de allegromicro.com
Mehrdad MaeenLecturer, Department of Computer Engineering, Yadegar Emam Khomeini Shahr e Rey BranchDirección de correo verificada de iausr.ac.ir
Mohammad Hossein MoaiyeriAssociate Professor of Electronics and Computer Engineering, Shahid Beheshti University, IranDirección de correo verificada de sbu.ac.ir
Majid MoghaddamAssistant Professor of Iranian Research Organization for Science and TechnologyDirección de correo verificada de irost.org
Hadi Tabatabaee MalaziAssistant professor of Computer Science, University College DublinDirección de correo verificada de ucd.ie
Alireza EjlaliAssociate Professor, Department of Computer Engineering, Sharif University of TechnologyDirección de correo verificada de sharif.edu
Georgi GaydadjievProfessor in Computer Architecture, University of GroningenDirección de correo verificada de rug.nl
Mahdi HosseynzadeUniversity of Human Development, Sulaymaniyah, Kurdistan Region of IraqDirección de correo verificada de uhd.edu.iq

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Somayeh Timarchi

Lecturer, University of hertfordshire - Shahid Beheshti University - TUDelft

Dirección de correo verificada de herts.ac.uk

Computer arithmetic Digital logic design Low power design Computer architecture


Título Ordenar por citas Ordenar por año Ordenar por título	Citado por Citado por	Año
Low-power and fast full adder by exploring new XOR and XNOR gates H Naseri, S Timarchi IEEE transactions on very large scale integration (VLSI) systems 26 (8 …, 2018	214	2018
Efficient Reverse Converter Designs for the New 4-Moduli Sets and Based on New CRTs AS Molahosseini, K Navi, C Dadkhah, O Kavehei, S Timarchi IEEE Transactions on Circuits and Systems I: Regular Papers 57 (4), 823-835, 2009	187	2009
A novel low-power full-adder cell for low voltage K Navi, M Maeen, V Foroutan, S Timarchi, O Kavehei Integration 42 (4), 457-467, 2009	165	2009
Arithmetic circuits of redundant SUT-RNS S Timarchi, K Navi IEEE Transactions on instrumentation and measurement 58 (9), 2959-2968, 2009	61	2009
An ultra-low-power 9T SRAM cell based on threshold voltage techniques M Moghaddam, S Timarchi, MH Moaiyeri, M Eshghi Circuits, Systems, and Signal Processing 35, 1437-1455, 2016	51	2016
Two efficient approximate unsigned multipliers by developing new configuration for approximate 4: 2 compressors L Sayadi, S Timarchi, A Sheikh-Akbari IEEE Transactions on Circuits and Systems I: Regular Papers 70 (4), 1649-1659, 2023	34	2023
Efficient class of redundant residue number system S Timarchi, K Navi 2007 IEEE international symposium on intelligent signal processing, 1-6, 2007	33	2007
Area–time–power efficient FFT architectures based on binary-signed-digit CORDIC H Mahdavi, S Timarchi IEEE Transactions on Circuits and Systems I: Regular Papers 66 (10), 3874-3881, 2019	27	2019
New Design of RNS Subtractor for modulo 2ⁿ+ 1 S Timarchi, K Navi, M Hosseinzade 2006 2nd International Conference on Information & Communication …, 2006	27	2006
Improved modulo 2n+ 1 adder design S Timarchi, K Navi International Journal of Electrical and Computer Engineering 2 (3), 472-479, 2008	21	2008
Low-power DCT-based compressor for wireless capsule endoscopy A Shabani, S Timarchi Signal Processing: Image Communication 59, 83-95, 2017	20	2017
Improving architectures of binary signed-digit CORDIC with generic/specific initial angles H Mahdavi, S Timarchi IEEE Transactions on Circuits and Systems I: Regular Papers 67 (7), 2297-2304, 2020	19	2020
High-speed energy-efficient 5: 2 compressor A Najafi, S Timarchi, A Najafi 2014 37th international convention on information and communication …, 2014	19	2014
A novel high-speed low-power binary signed-digit adder S Timarchi, P Ghayour, A Shahbahrami The 16th CSI International Symposium on Computer Architecture and Digital …, 2012	16	2012
Area-time-efficient scalable schoolbook polynomial multiplier for lattice-based cryptography YA Birgani, S Timarchi, A Khalid IEEE Transactions on Circuits and Systems II: Express Briefs 69 (12), 5079-5083, 2022	13	2022
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n− 1, 2n, 2n+ 1} S Timarchi, M Fazlali IET computers & digital techniques 6 (5), 269-276, 2012	13	2012
A unified addition structure for moduli set {2ⁿ−1, 2ⁿ, 2ⁿ+1} based on a novel RNS representation S Timarchi, M Fazlali, SD Cotofana 2010 IEEE International Conference on Computer Design, 247-252, 2010	13	2010
Efficient approximate multiplier based on a new 1-gate approximate compressor SAH Ejtahed, S Timarchi Circuits, Systems, and Signal Processing, 1-20, 2022	12	2022
Fast architecture for decimal digit multiplication M Fazlali, H Valikhani, S Timarchi, HT Malazi Microprocessors and Microsystems 39 (4-5), 296-301, 2015	12	2015
Design of Residue Number System Circuits in Current mode M Hosseinzadeh, K Navi, S Timarchi Proc. 14th Iranian Conference of Electrical Engineering, 2006	12	2006

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