| Conclusively verifying clock-domain crossings in very large hardware designs G Plassan, HJ Peter, K Morin-Allory, F Rahim, S Sarwary, D Borrione 2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016 | 5 | 2016 |
| Improving the efficiency of formal verification: the case of clock-domain crossings G Plassan, HJ Peter, K Morin-Allory, S Sarwary, D Borrione VLSI-SoC: System-on-Chip in the Nanoscale Era–Design, Verification and …, 2017 | 4 | 2017 |
| Conclusive formal verification of clock domain crossings using spyglass-cdc M Kebaïli, G Plassan, JC Brignone, JP Binois SNUG France, 2016 | 4 | 2016 |
| Extraction of missing formal assumptions in under-constrained designs G Plassan, K Morin-Allory, D Borrione Proceedings of the 15th ACM-IEEE International Conference on Formal Methods …, 2017 | 3 | 2017 |
| Formal clock network analysis, visualization, verification and generation MS Sarwary, HJ Peter, G Plassan, B Chakrabarti, MH Movahed-ezazi US Patent 10,599,800, 2020 | 2 | 2020 |
| Mining missing assumptions from counter-examples G Plassan, K Morin-Allory, D Borrione ACM Transactions on Embedded Computing Systems (TECS) 18 (1), 1-25, 2019 | 2 | 2019 |
| Conclusive formal verification of clock domain crossing properties G Plassan Université Grenoble Alpes, 2018 | 1 | 2018 |
| Formal gated clock conversion for field programmable gate array (FPGA) synthesis L McIlwain, F Rahim, G Plassan, DR Senapati US Patent 11,526,641, 2022 | | 2022 |
Dominique BorrioneRetired Professor from UGA, GrenobleDirección de correo verificada de imag.fr
