High-performance junctionless MOSFETs for ultralow-power analog/RF applications D Ghosh, MS Parihar, GA Armstrong, A Kranti
IEEE Electron Device Letters 33 (10), 1477-1479, 2012
113 2012 Ultra low power junctionless MOSFETs for subthreshold logic applications MS Parihar, D Ghosh, A Kranti
IEEE Transactions on Electron Devices 60 (5), 1540-1546, 2013
99 2013 Enhanced sensitivity of double gate junctionless transistor architecture for biosensing applications MS Parihar, A Kranti
Nanotechnology 26 (14), 145201, 2015
69 2015 A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters S Cristoloveanu, KH Lee, MS Parihar, H El Dirani, J Lacord, S Martinie, ...
Solid-State Electronics 143, 10-19, 2018
56 2018 Revisiting the doping requirement for low power junctionless MOSFETs MS Parihar, A Kranti
Semiconductor Science and Technology 29 (7), 075006, 2014
51 2014 The concept of electrostatic doping and related devices S Cristoloveanu, KH Lee, H Park, MS Parihar
Solid-State Electronics 155, 32-43, 2019
50 2019 Single transistor latch phenomenon in junctionless transistors M Singh Parihar, D Ghosh, A Kranti
Journal of Applied Physics 113 (18), 2013
45 2013 Bipolar effects in unipolar junctionless transistors MS Parihar, D Ghosh, GA Armstrong, R Yu, P Razavi, A Kranti
Applied Physics Letters 101 (9), 2012
45 2012 C Navarro, M Duan, MS Parihar, F Adamu-Lema, S Coseman, J Lacord, ...
IEEE Transactions on Electron Devices 64 (12), 4904-4909, 2017
35 2017 Bipolar snapback in junctionless transistors for capacitorless dynamic random access memory M Singh Parihar, D Ghosh, G Alastair Armstrong, A Kranti
Applied Physics Letters 101 (26), 2012
33 2012 A comprehensive model on field-effect pnpn devices (Z2-FET) Y Taur, J Lacord, MS Parihar, J Wan, S Martinie, K Lee, M Bawedin, ...
Solid-State Electronics 134, 1-8, 2017
22 2017 Low-power Z2-FET capacitorless 1T-DRAM MS Parihar, KH Lee, H El Dirani, C Navarro, J Lacord, S Martinie, ...
2017 IEEE International Memory Workshop (IMW), 1-4, 2017
18 2017 Insight into carrier lifetime impact on band-modulation devices MS Parihar, KH Lee, HJ Park, J Lacord, S Martinie, JC Barbé, Y Xu, ...
Solid-State Electronics 143, 41-48, 2018
17 2018 Volume accumulated double gate junctionless MOSFETs for low power logic technology applications MS Parihar, A Kranti
Fifteenth international symposium on quality electronic design, 335-340, 2014
17 2014 Competitive 1T-DRAM in 28 nm FDSOI technology for low-power embedded memory H El Dirani, M Bawedin, K Lee, M Parihar, X Mescot, P Fonteneau, P Galy, ...
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2016
16 2016 Back bias induced dynamic and steep subthreshold swing in junctionless transistors MS Parihar, A Kranti
Applied Physics Letters 105 (3), 2014
16 2014 MSDRAM, A2RAM and Z2 -FET performance benchmark for 1T-DRAM applications J Lacord, MS Parihar, C Navarro, FT Wakam, M Bawedin, S Cristoloveanu, ...
2018 International Conference on Simulation of Semiconductor Processes and …, 2018
14 2018 Ultra-low power 1T-DRAM in FDSOI technology H El Dirani, KH Lee, MS Parihar, J Lacord, S Martinie, JC Barbe, X Mescot, ...
Microelectronic Engineering 178, 245-249, 2017
14 2017 Back-gate effects and detailed characterization of junctionless transistor MS Parihar, FY Liu, C Navarro, S Barraud, M Bawedin, I Ionica, A Kranti, ...
2015 45th European Solid State Device Research Conference (ESSDERC), 282-285, 2015
11 2015 Back-gate effects and mobility characterization in junctionless transistor MS Parihar, F Liu, C Navarro, S Barraud, M Bawedin, I Ionica, A Kranti, ...
Solid-State Electronics 125, 154-160, 2016
10 2016 