Paolo Faraboschi

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Citations	5658	2009
h-index	37	22
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Dejan MilojicicHewlett Packard LabsVerified email at hpe.com
Joseph A (Josh) FisherHP Senior Fellow EmeritusVerified email at vliw.org
Giuseppe DesoliSTMicroelectronics, HewlettPackardVerified email at st.com
Ayose FalcónHPVerified email at hp.com
John Paul StrachanDirector, Peter Grünberg Institute for Neuromorphic Compute Nodes; Professor RWTH AachenVerified email at fz-juelich.de
Cliff YoungGoogle BrainVerified email at post.harvard.edu
Mauro OlivieriSapienza University of Rome, Italy. - Barcelona Supercomputing Center, Spain.Verified email at uniroma1.it
sai rahul chalamalasettiHewlett Packard LabsVerified email at hpe.com
Geoffrey M BrownIndiana UniversityVerified email at indiana.edu
Izzat El HajjAmerican University of BeirutVerified email at aub.edu.lb
Abhishek GuptaFacebook, Visiting faculty - Santa Clara University, PhD UIUCVerified email at illinois.edu
Wen-mei W. HwuSenior Distinguished Research Scientist, NVIDIA; Professor and Sanders-AMD Chair of Electrical andVerified email at illinois.edu
Eitan FrachtenbergVerified email at frachtenberg.org
Phillip Laplantepenn state/NISTVerified email at psu.edu
Sheng LiGoogleVerified email at google.com
Laxmikant KaleProfessor or Computer Science, University of IllinoisVerified email at illinois.edu
Cong XuResearch Scientist, Hewlett Packard LabsVerified email at hpe.com
Evelyn DuesterwaldIBM ResearchVerified email at us.ibm.com
Kaushik RoyProfessor of Electrical and Computer Engineering, Purdue UniversityVerified email at purdue.edu
Aayush AnkitHardware Architect, d-MatrixVerified email at d-matrix.ai

Paolo Faraboschi

Hewlett Packard Labs

Verified email at faraboschi.com - Homepage

exascale SoC vliw computer architecture AI and machine learning


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Embedded computing: a VLIW approach to architecture, compilers and tools JA Fisher, P Faraboschi, C Young Elsevier, 2005	516	2005
Lx: a technology platform for customizable VLIW embedded processing P Faraboschi, G Brown, JA Fisher, G Desoli, F Homewood ISCA27 and ACM SIGARCH Computer Architecture News 28 (2), 203-213, 2000	474	2000
PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference A Ankit, IE Hajj, SR Chalamalasetti, G Ndu, M Foltin, RS Williams, ... Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019	380	2019
COTSon: infrastructure for full system simulation E Argollo, A Falcón, P Faraboschi, M Monchiero, D Ortega ACM SIGOPS Operating Systems Review 43 (1), 52-61, 2009	276	2009
Operating System Support for NVM+ DRAM Hybrid Main Memory. JC Mogul, E Argollo, MA Shah, P Faraboschi HotOS 9, 14-14, 2009	265	2009
Hardware solutions for fuzzy control A Costa, A De Gloria, P Faraboschi, A Pagni, G Rizzotto Proceedings of the IEEE 83 (3), 422-434, 1995	134	1995
HPC-aware VM placement in infrastructure clouds A Gupta, LV Kale, D Milojicic, P Faraboschi, SM Balle 2013 IEEE International Conference on Cloud Engineering (IC2E), 11-20, 2013	133	2013
Main memory with non-volatile memory and DRAM JC Mogul, EA de Oliveira Dias Jr, P Faraboschi, MA Shah US Patent 8,296,496, 2012	129	2012
Custom-fit processors: Letting applications define architectures JA Fisher, P Faraboschi, G Desoli Proceedings of the 29th Annual IEEE/ACM International Symposium on …, 1996	128	1996
Deli: A new run-time control point G Desoli, N Mateev, E Duesterwald, P Faraboschi, JA Fisher 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002	126	2002
The who, what, why, and how of high performance computing in the cloud A Gupta, LV Kale, F Gioachin, V March, CH Suen, BS Lee, P Faraboschi, ... 2013 IEEE 5th international conference on cloud computing technology and …, 2013	116	2013
Evaluating and improving the performance and scheduling of HPC applications in cloud A Gupta, P Faraboschi, F Gioachin, LV Kale, R Kaufmann, BS Lee, ... IEEE Transactions on Cloud Computing 4 (3), 307-321, 2014	109	2014
Beyond processor-centric operating systems P Faraboschi, K Keeton, T Marsland, D Milojicic 15th Workshop on Hot Topics in Operating Systems (HotOS XV), 2015	104	2015
The latest word in digital and media processing P Faraboschi, G Desoli, JA Fisher IEEE signal processing magazine 15 (2), 59-85, 1998	103	1998
TERAFLUX: Harnessing dataflow in next generation teradevices R Giorgi, RM Badia, F Bodin, A Cohen, P Evripidou, P Faraboschi, ... Microprocessors and Microsystems 38 (8), 976-990, 2014	89	2014
Instruction scheduling for instruction level parallel processors P Faraboschi, JA Fisher, C Young Proceedings of the IEEE 89 (11), 1638-1659, 2001	88	2001
How to simulate 1000 cores M Monchiero, JH Ahn, A Falcón, D Ortega, P Faraboschi ACM SIGARCH Computer Architecture News 37 (2), 10-19, 2009	84	2009
Method for storing and decoding instructions for a microprocessor having a plurality of function units P Faraboschi, P Raje US Patent 5,930,508, 1999	84	1999
Methods, Apparatus and Software for Validating Entries Made on a Form P Faraboschi, A Mackenzie US Patent App. 11/659,012, 2008	78	2008
Clustered instruction-level parallel processors P Faraboschi, G Desoli, JA Fisher Hewlett Packard Laboratories, 1999	78	1999

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