| Cvc4 CC Clark Barrett, M Deters, L Hadarean, D Jovanovic, T King, A Reynolds, ... 23rd International Conference on Computer Aided Verification (CAV’11) 6806 …, 2011 | 2138* | 2011 |
| cvc5: A versatile and industrial-strength SMT solver H Barbosa, C Barrett, M Brain, G Kremer, H Lachnitt, M Mann, ... International Conference on Tools and Algorithms for the Construction and …, 2022 | 447 | 2022 |
| Counterexample-guided quantifier instantiation for synthesis in SMT A Reynolds, M Deters, V Kuncak, C Tinelli, C Barrett Computer Aided Verification: 27th International Conference, CAV 2015, San …, 2015 | 182 | 2015 |
| A DPLL(T) Theory Solver for a Theory of Strings and Regular Expressions T Liang, A Reynolds, C Tinelli, C Barrett, M Deters Computer Aided Verification: 26th International Conference, CAV 2014, Held …, 2014 | 167 | 2014 |
| Induction for SMT solvers A Reynolds, V Kuncak International Workshop on Verification, Model Checking, and Abstract …, 2015 | 131 | 2015 |
| SMTCoq: A plug-in for integrating SMT solvers into Coq B Ekici, A Mebsout, C Tinelli, C Keller, G Katz, A Reynolds, C Barrett Computer Aided Verification: 29th International Conference, CAV 2017 …, 2017 | 118 | 2017 |
| Quantifier instantiation techniques for finite model finding in SMT A Reynolds, C Tinelli, A Goel, S Krstić, M Deters, C Barrett Automated Deduction–CADE-24: 24th International Conference on Automated …, 2013 | 95 | 2013 |
| Finding conflicting instances of quantified formulas in SMT A Reynolds, C Tinelli, L De Moura 2014 Formal Methods in Computer-Aided Design (FMCAD), 195-202, 2014 | 92 | 2014 |
| SMT proof checking using a logical framework A Stump, D Oe, A Reynolds, L Hadarean, C Tinelli Formal Methods in System Design 42, 91-118, 2013 | 86 | 2013 |
| Finite model finding in SMT A Reynolds, C Tinelli, A Goel, S Krstić Computer Aided Verification: 25th International Conference, CAV 2013, Saint …, 2013 | 82 | 2013 |
| cvc4sy: Smart and Fast Term Enumeration for Syntax-Guided Synthesis A Reynolds, H Barbosa, A Nötzli, C Barrett, C Tinelli Computer Aided Verification: 31st International Conference, CAV 2019, New …, 2019 | 81 | 2019 |
| Revisiting enumerative instantiation A Reynolds, H Barbosa, P Fontaine Tools and Algorithms for the Construction and Analysis of Systems: 24th …, 2018 | 75 | 2018 |
| An efficient SMT solver for string constraints T Liang, A Reynolds, N Tsiskaridze, C Tinelli, C Barrett, M Deters Formal Methods in System Design 48, 206-234, 2016 | 70 | 2016 |
| A tour of CVC4: how it works, and how to use it M Deters, A Reynolds, T King, C Barrett, C Tinelli 2014 Formal Methods in Computer-Aided Design (FMCAD), 7-7, 2014 | 63 | 2014 |
| Extending SMT solvers to higher-order logic H Barbosa, A Reynolds, D El Ouraoui, C Tinelli, C Barrett Automated Deduction–CADE 27: 27th International Conference on Automated …, 2019 | 60* | 2019 |
| A decision procedure for (co) datatypes in SMT solvers A Reynolds, JC Blanchette Journal of Automated Reasoning 58, 341-362, 2017 | 55 | 2017 |
| A decision procedure for separation logic in SMT A Reynolds, R Iosif, C Serban, T King International Symposium on Automated Technology for Verification and …, 2016 | 53 | 2016 |
| Solving quantified bit-vectors using invertibility conditions A Niemetz, M Preiner, A Reynolds, C Barrett, C Tinelli International Conference on Computer Aided Verification, 236-255, 2018 | 51 | 2018 |
| Scaling up DPLL (T) string solvers using context-dependent simplification A Reynolds, M Woo, C Barrett, D Brumley, T Liang, C Tinelli International Conference on Computer Aided Verification, 453-474, 2017 | 49 | 2017 |
| Solving quantified linear arithmetic by counterexample-guided instantiation A Reynolds, T King, V Kuncak Formal Methods in System Design 51, 500-532, 2017 | 48* | 2017 |
Cesare TinelliProfessor of Computer Science, The University of IowaVerified email at uiowa.edu
